Lift-Off: Technique
What if you do not know the suitable etchant, but you still want to pattern thin films?
For thin films, such as metal, we can use the lift-off process.
Thick $(5 \mu m)$ negative PR is usually used.
Organic solvent such as acetone is usually used to dissolve the PR. We can also perform multiple-layer deposition by lift-off.
The lift-off technique refers to the process of exposing a pattern into photoresist (or some other material), depositing a thin film (such as a metal of dielectric) over the entire area, then washing away the photoresist (or other material) to leave behind the film only in the patterned area.
Toluene Soak
Before developing the photoresist, after exposure, you can soak the sample in Toluene for 5 minutes.
This creates a hardened layer in the photoresist surface that resists developing. A deep UV exposure can also lead to this effect.
Once hardened, you can develop the resist with a slightly longer than normal time.
Negative/Image Reversal Resist
By using a negative resist and adjusting the exposure and develop time, one can obtain a retrograde profile.
This is much better for lift-off than positive resist which gives a straight or slightly graded profile.
Remember, with a negative resist, less exposure means more developer attack which means more undercut.
Bi-layer
By using two different types of resist on top of each other, one can precisely pattern the top resist and then undercut the bottom resist to form a very nice lift-off profile.
You must use resists with different solvents/chemistries to avoid intermixing which will make the process inconsistent
PMGI, Shipley LOL, and LOR series resists work well as underlayers for i-line and broad-band lithography. With PMGI, the resist serves as a mask for DUV (250nm) exposure and development of the PMGI.
The Shipley LOL and the LOR resists use bake temperature to control undercut rate using standard resist developers. The top layer can be positive or negative tone and, you can lift-off up to ~2/3 of the bttom layer thickness.
This process allows for very clean lift-off using positive tone resist. Lift-off is performed in resist strippers.
LOR is not optically sensitive, isotropically etched in developer and etch rate depends on LOR soft bake temp.
Mask Design
By adding the ‘alignment marks’ on the masks, fabrication of different layers can align to the right positions.
We have the following alignment operations:
- Wafer with alignment marks.
- Photomask with alignment marks
- After linear translation and rotation of the wafer the alignment marks on wafer and mask coincide.
Example: Microfabrication of a Cantilever
On the silicon substrate is formed a silicon dioxide layer, whose tickness will determine the gap size for the cantilevered member.
Portions of the SiO$_2$ layer are etched using lithography.
A polysilicon layer is applied.
Portions of the polysilicon layers are etched using lithography.
Finally, the SiO$_2$ layer beneath the cantilevers is selectively etched.
Detailed Process Flow
- Piranha Clean Wafer
- Grow SiO$_2$ by oxidation.
- Spincoat PR.
- Pattern photolithography on PR.
- Dry etch SiO2 using RIE with CF4 gas.
- Remove RP using acetone.
- PECVD Poly-Si.
- Spincoat PR.
- Pattern PR by photolithography.
- Etch Poly-Si using RIE with SF6 gas.
- Remove PR using acetone
- Remove SiO2 thoroughly by 4.9%
Nanoimprint Lithography (NIL)
Is a new technology taht makes very small features for integrated circuits.
Better than photolithography because it can achieve smaller features. Better than electron beam lithography because it takes les time to produce.
The method to do nanoimprint lithography is practical and fast. Nanoimprint is one method of the future of lithography.
Nanoimprint Process
- Press in mold.
- Heat up mold and substrate.
- Mold separation after cooling.
- O$_2$ RIE (Reactive Ion Etching) to remove residual layer.
Pattern Transfer
- Grating pattern in resist.
- Cr evaporation.
- Lift-off.
- CHF$_3$ and O$_2$ RIE.
Thermal VS. UV NIL
- Thermal NIL
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+: Less restricitions on template
- Si and Ni are okay.
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+: Simpler/cleaner process.
- UV resists are little ‘messy’.
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-: More readily availble poly/resists.
-
-: Temperature (but, controllable)
- May be as high as 200$^\circ$C.
- CTE (Coefficient of Thermal Expansion) mismatch between template and wafer.
- Distortion of alignment, function of substrate size.
-
-: May require large force
- Another source of distortion.
- Breakage.
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- UV NIL
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+: No thermal cycling.
- No CTE (Coefficient of Thermal Expansion) mismatch.
-
+ Fast (few seconds).
-
+ Usually minimal force needed.
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-: Volume shrinkage due to phase transition.
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-: Uniform layers from spin coating.
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-: Must use transparent template.
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Antistick
Antistick layers are used to prevent the resist from sticking to the template. This is crucial for UV NIL. Otherwise, the resist will stick to the template and not the wafer.
Imprinting in Presence of a Particle (Contamination)
If there is contamination on the wafer or resist itself, the imprinting process will be affected.
If there is contamination under the wafer, the wafer may even crack.